The present disclosure relates to semiconductor devices, and in particular, to a chip-on-chip (CoC) semiconductor device.
There is an increasing demand that semiconductor devices decrease in size and thickness while providing improved performance. As an example of semiconductor devices meeting the demand, CoC semiconductor devices, in which functional surfaces of chips are joined by means of joint members such as bumps, have become widespread. In the CoC semiconductor devices, it is possible to increase the speed of signal control between upper and lower chips and to combine chips having been produced by different processes. The CoC semiconductor devices thus have high versatility.
Japanese Unexamined Patent Publication No. 2004-146728 describes a CoC semiconductor device.
The conventional semiconductor device described in Japanese Unexamined Patent Publication No. 2004-146728 includes a motherboard, a first chip placed above the motherboard, and a second chip placed above the first chip.
The first chip is in connection to the second chip through solder bumps. The second chip (i.e. the upper chip) is larger in size than the first chip (i.e. the lower chip), and has the peripheral portion projecting laterally relative to the side faces of the first chip. The projecting peripheral portion of the second chip is in connection to the motherboard through solder electrodes.
The function of the first chip is utilized from the motherboard through the solder bumps connecting the first chip to the second chip, interconnects within the second chip, and the solder electrodes connecting the second chip to the motherboard. The function of the second chip is utilized from the motherboard through the solder electrodes connecting the second chip to the motherboard.